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Section: Partnerships and Cooperations
Regional Initiatives
Function field sieve: implementation and hardware acceleration
Participants : Jérémie Detrey [contact] , Pierrick Gaudry, Hamza Jeljeli, Emmanuel Thomé.
The team has obtained for the years 2012 and 2013 a financial support from the Région Lorraine and Inria for a project focusing on the hardware implementation and acceleration of the function field sieve (FFS).
The FFS algorithm is currently the best known method to compute discrete logarithms in small-characteristic finite fields, such as may occur in pairing-based cryptosystems. Its study is therefore crucial to accurately assess the key-lengths which such cryptosystems should use. More precisely, this project aims at quantifying how much this algorithm can benefit from recent hardware technologies such as GPUs or CPU-embedded FPGAs, and how this might impact current key length recommendations.
While the more FPGA-related aspects of this project were put on hold in 2013, the GPU option was explored further. To this end, eight NVIDIA GeForce GTX 680 graphics cards were bought and installed in four nodes connected by an InfiniBand. Hamza Jeljeli was able to extend his GPU implementation of sparse linear algebra routines so as to take multi-GPU and multi-node computations into account. This setup was for instance used to break the discrete-logarithm record over an 809-bit binary field [15] .